1. Field of the Invention
The present invention relates to a dynamic semiconductor integrated circuit used in a decoder circuit such as a memory circuit and a matching detection circuit. In particular, the present invention relates to a technique for speeding up a semiconductor integrated circuit in which a NAND dynamic circuit is connected to a NOR dynamic circuit. Furthermore, the present invention relates to a circuit arrangement technique for preventing degradation of the transistor characteristics in such a semiconductor integrated circuit.
2. Description of the Related Art
In a decoder circuit such as a memory circuit that is synchronized with a clock, in order to increase speed, a NAND dynamic circuit has been used so as to reduce the number of logic stages and the capacity of a gate of a decoder circuit with a static configuration. In a matching detection circuit for comparing a plurality of data with each other to detect whether or not they are matched, used in a comparison portion of a translation lookaside buffer (TLB) and a tag part of a cache, in order to increase speed, a differential sense amplifier system for comparing voltage differences has been used. Examples of the sense amplifier system include circuit systems described in JP 10(1998)-27481 A and JP 2000-251479 A. The above-mentioned circuits are those of a latch type for holding data only in a logic xe2x80x9cHxe2x80x9d level period or a logic xe2x80x9cLxe2x80x9d level period of a clock.
Examples of a flip-flop circuit increasing speed, for holding output data of a decoder circuit or a matching detection circuit during one period of a clock, include those described in xe2x80x9cA rue Single-Phase-Clock Dynamic CMOS Circuit Techniquexe2x80x9d (YUAN JI-REN et al.) in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.SC-22, NO.5, OCTOBER 1987 and xe2x80x9cA New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processorsxe2x80x9d (Fabian Klass et al.) in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999.
In the case of the above-mentioned conventional configuration, along with miniaturization of a semiconductor, a power source voltage is lowered only with a NAND dynamic circuit. Therefore, in order to maintain speed increases, there is a limit to the number of serial stages. Furthermore, according to the method of YAN JI-REN et al. and Fabian Klass et al. in which a NAND dynamic circuit is connected to an output of a NOR dynamic circuit, when an input element of the NOR dynamic circuit is at a logic xe2x80x9cLxe2x80x9d level, during a period in which a clock transitions from a logic xe2x80x9cLxe2x80x9d level to a logic xe2x80x9cHxe2x80x9d level, an output node of the NOR dynamic circuit is in a floated state, an output of the NAND dynamic circuit of a subsequent stage becomes a logic xe2x80x9cLxe2x80x9d level, and a coupling capacitance formed between the output node of the NOR dynamic circuit and the NAND dynamic circuit holds a charge. Therefore, the output voltage of the NOR dynamic circuit is lowered, and the operation speed is degraded.
Furthermore, in the matching detection circuit using an analog element, when a device area is decreased, the variation in characteristics of an element is increased in accordance with a scaling rule of miniaturization, and an operation becomes unstable. On the other hand, when the operation of an element is stabilized, wiring and the like becomes long due to an increased area of a device, which makes it difficult to realize increased speed.
Another problem is caused along with miniaturization of a semiconductor. More specifically, when a shallow trench insulator (STI) is formed in a semiconductor substrate so as to separate transistors or circuit blocks, a lattice constant of a molecular structure that is a characteristic of a diffusion region constituting a source or a drain of a MOS transistor is distorted Because of this, stress is applied to the diffusion region of a transistor formed in a region close to the STI. Consequently, charge mobility is decreased, a current ability (Ids) is lowered, and a threshold voltage (Vth) is increased. More specifically, the characteristics of transistors close to the STI and transistors, in which an interval of a diffusion capacity portion between the transistors is small, are degraded.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor integrated circuit in which increased speed is realized by a system in which a NAND dynamic circuit is connected to a NOR dynamic circuit, glitches occurring in an output of the NAND dynamic circuit are reduced to realize a stable operation and low power consumption, and transistor characteristics are prevented from being degraded by a miniaturization process.
In order to achieve the above-mentioned object, a first semiconductor integrated circuit of the present invention includes: a NOR dynamic circuit for receiving a first clock (CLK1) and a plurality of first data (ADR [0-4], holding a charge of a first output node in a case where during one of a period from rising to falling of the first clock and a period from falling to rising of the first clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and discharging the first output node in a case where at least one of the plurality of first data is not matched; a NAND dynamic circuit for receiving a second dock (CLK2, CLK3) and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second clock and a period from falling to rising of the second dock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held; and a compensating circuit for compensating for a voltage drop of the first output node, which is caused by a coupling capacitance formed between the first output node and the second output node, which occurs when the second output node is discharged while the charge of the first output node is held
According to the above-mentioned configuration, the number of logic stages is reduced, compared with a decoder entirely composed of static circuits. Furthermore, due to the NAND dynamic circuit, compared with the case where a static NAND circuit is provided, the load capacity of a gate that receives a second dock and the load capacity of a gate of the NAND dynamic circuit connected to the output node of the NOR dynamic circuit are reduced. Furthermore, a voltage drop of the output node of the NOR dynamic circuit is compensated by the compensating circuit, whereby an operation speed can be increased.
In the first semiconductor integrated circuit, it is preferable that the compensating circuit includes a feedback circuit for charging the first output node in a case where the second output node is discharged.
According to the above-mentioned configuration, while a signal of the output node of the NAND dynamic circuit transitions from a logic xe2x80x9cHxe2x80x9d level to a logic xe2x80x9cLxe2x80x9d level, a voltage drop due to a coupling capacitance is compensated, and a voltage level of the output node of the NOR dynamic circuit can be increased, whereby increased speed can be realized.
In the first semiconductor integrated circuit, it is preferable that the NOR dynamic circuit includes: a first N-type MOS transistor in which a gate is supplied with the first clock and a source is grounded; a first P-type MOS transistor in which a gate is supplied with the first dock and a source is connected to a power source; and a plurality of second N-type MOS transistors in which gates are supplied with the plurality of first data, sources are connected to a drain of the first-N-type MOS transistor and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed.
According to the above-mentioned configuration, the number of serial stages of each transistor is two or less, and increased speed can be realized even at a low voltage.
In the first semiconductor integrated circuit, it is preferable that the compensating circuit includes a P-type MOS transistor in which a gate is connected to a second output node of the NAND dynamic circuit, a source is connected to a power source, and a drain is connected to a first output node of the NOR dynamic circuit.
According to the above-mentioned configuration, the output node of the NOR dynamic circuit is charged by receiving a signal of the output node of the NAND dynamic circuit, which transitions the P-type MOS transistor from a logic xe2x80x9cHxe2x80x9d level to a logic xe2x80x9cLxe2x80x9d level, whereby a voltage drop due to a coupling capacitance is compensated, and a voltage level of the output node of the NOR dynamic circuit can be increased, whereby increased speed can be realized.
In the first semiconductor integrated circuit, it is preferable that the compensating circuit includes: an inverter in which an input terminal is connected to a second output node of the NAND dynamic circuit; and an N-25 type MOS transistor in which a gate is connected to an output terminal of the inverter, and a source and a drain are connected in common to the first output node of the NOR dynamic circuit.
According to the above-mentioned configuration, a voltage drop of the output node of the NOR dynamic circuit due to a coupling capacitance can be compensated. In addition, by decreasing a ratio between the fan-in and fan-out of the inverter, the through rate of the output of the inverter can be made very steep, and the voltage of the output node in the NOR dynamic circuit can be raised instantaneously, whereby further speed increases can be realized.
In order to achieve the above-mentioned object, a second semiconductor integrated circuit of the present invention includes: a NOR dynamic circuit for receiving a first clock (CLK1) and a plurality of first data (ADR[0-4]), holding a charge of a first output node in a case where during one of a period from rising to falling of the first clock and a period from falling to rising of the first clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and discharging the first output node in a case where at least one of the plurality of first data is not matched, and a NAND dynamic circuit for receiving a second clock (CLK2, CLK3) and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second clock and a period from falling to rising of the second clock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held, wherein the first clock is in phase with the second dock or the first clock is identical with the second clock, and rising times of the first and second clocks are longer than a discharge time of the first output node of the NOR dynamic circuit.
In the second semiconductor integrated circuit, it is preferable that the second clock is subjected to control for beginning and suspension of supply.
According to the above-mentioned configuration, even in the case where the load capacity of the output node of the NOR dynamic circuit is large, glitches occurring in the output of the NAND dynamic circuit can be reduced, and a stable operation and low power consumption can be made possible with only a clock of one system.
It is preferable that the second semiconductor integrated circuit includes a second NOR dynamic circuit, and an inverter in which an input terminal is connected to a third output node of the second NOR dynamic circuit, and the second clock is supplied from an output terminal, wherein the second NOR dynamic circuit includes: a third N-type MOS transistor in which a gate is supplied with the first clock and a source is grounded; a second P-type MOS transistor in which a gate is supplied with the first clock and a source is connected to a power source; and a plurality of fourth N-type MOS transistors in which one gate is connected to a power source, the remaining gates are grounded, sources are connected to a drain of the third N-type transistor, and drains are connected to a drain of the second P-type MOS transistor, whereby the third output node is formed. In this case, among the plurality of fourth N-type MOS transistors, an N-type MOS transistor in which a gate is connected to a power source is for example positioned farthest from the input terminal of the inverter in physical arrangement.
According to the above-mentioned configuration, a current path between the power source and the ground of the NAND dynamic circuit is cut off, and a leakage current is prevented, whereby glitches can be reduced. Accordingly, even in the case where the load capacity of the output node of the NOR dynamic circuit is large, a stable operation and low power consumption can be made possible.
In the first and second semiconductor integrated circuits, it is preferable that the NOR dynamic circuit includes: a first P-type MOS transistor in which a gate is supplied with the first clock and a source is connected to a power source; a switching circuit for receiving a ground potential and the plurality of first data, selectively outputting the ground potential while the first output node of the NOR dynamic circuit is charged, and thereafter, selectively outputting the plurality of data; and a plurality of N-type MOS transistors in which gates are supplied with an output signal of the switching circuit, sources are grounded, and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed.
According to the above-mentioned configuration, unlike a general NOR dynamic circuit, a junction capacity and wiring are not required, and the number of serial stages is reduced, whereby a high-speed operation can be conducted even at a lower voltage.
The first and second semiconductor integrated circuits include a matching detection circuit, wherein the matching detection circuit receives one of a plurality of second data and one of a plurality of third data, detects whether or not the data are matched with each other, and outputs a detection result as the plurality of first data.
According to the above-mentioned configuration, a matching detection circuit capable of being operated at a high speed can be realized in a semiconductor integrated circuit.
In the first and second semiconductor integrated circuits, it is preferable that the second clock is composed of a clock for charging the second output node of the NAND dynamic circuit and a clock for discharging the second output node, the clock for charging is the same as the first clock, and a rising time of the clock for discharging is longer than a discharge time of the first output node of the NOR dynamic circuit.
According to the above-mentioned configuration, even in the case where the load capacity of the output node of the NOR dynamic circuit is large, a stable operation and low power consumption can be made possible, whereby further speed increases can be realized.
In the first and second semiconductor integrated circuits, it is preferable that the NAND dynamic circuit charges the second output node during one of a period from rising to falling of the second clock and a period from falling to rising of the second clock, and holds the charge of the second output node during a half period of the second clock.
The above-mentioned configuration is suitable for a circuit system characterized by a latch configuration such as an SRAM.
It is preferable that the first and second semiconductor integrated circuits include a positive feedback circuit in which inverters are connected in a cascade, and an output terminal of the inverter in a final stage is connected to an input terminal of the inverter in a first stage and the second output node of the NAND dynamic circuit, wherein the positive feedback circuit holds the charge of the second output node during one period of the second clock.
The above-mentioned configuration is suitable for a circuit system characterized by a flip-flop configuration.
In the first and second semiconductor integrated circuits, the first clock and the second dock may have different duty ratios, and voltage levels of the first clock and the second clock may be lower than operation voltages of the NOR dynamic circuit and the NAND dynamic circuit.
According to the above-mentioned configuration, the amplitude of a clock can be made lower, and low power consumption can be realized
It is preferable that the first and second semiconductor integrated circuits include a second NOR dynamic circuit, and an inverter in which an input terminal is connected to a third output node of the second NOR dynamic circuit and the second clock is supplied from an output terminal, wherein the second NOR dynamic circuit includes: a second P-type MOS transistor in which a gate is supplied with the first clock and a source is connected to a power source; a switching circuit for receiving a power source potential and a ground potential, selectively outputting the ground potential while the first output node of the NOR dynamic circuit is charged, and thereafter, selectively outputting the power source potential; a third P-type MOS transistor in which a gate is supplied with an output signal of the switching circuit, a source is grounded, and a drain is connected to a drain of the second P-type MOS transistor; and a plurality of fourth N-type MOS transistors in which a gate and a source are grounded and a drain is connected to a drain of the second P-type MOS transistor.
According to the above-mentioned configuration, a current path between the power source and the ground of the NAND dynamic circuit is cut off, and a leakage current is prevented, whereby glitches can be reduced. Accordingly, even in the case where the load capacity of the output node of the NOR dynamic circuit is large, a stable operation and low power consumption can be made possible.
In order to achieve the above-mentioned object, a third semiconductor integrated circuit of the present invention includes a first NOR dynamic circuit including: a first P-type MOS transistor in which a gate is supplied with a first clock (CLK1) and a source is connected to a power source; a first switching circuit for receiving a ground potential and a plurality of first data (A, B, C, D), selectively outputting the ground potential while the first output node is charged, and thereafter, selectively outputting the plurality of data; and a plurality of first N-type MOS transistors in which gates are supplied with an output signal of the first switching circuit, sources are grounded, and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed, in order to receive the first clock and the plurality of first data, to hold the charge of the first output node in a case where during one of a period from rising to falling of the first dock and a period from falling to rising of the first clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and to discharge the first output node in a case where at least one of the plurality of first data is not matched The third semiconductor integrated circuit of the present invention also includes a NAND dynamic circuit for receiving a second clock (CLK2, CLK3) and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second dock and a period from falling to rising of the second dock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held. The third semiconductor integrated circuit of the present invention also includes a second NOR dynamic circuit including: a second P-type MOS transistor in which a gate is supplied with the first clock, and a source is connected to a power source; a second switching circuit for receiving a power source potential and a ground potential, selectively outputting the ground potential while the first output node of the first NOR dynamic circuit is charged, and thereafter, selectively outputting the power source potential; a second N-type MOS transistor in which a gate is supplied with an output signal from the second switching circuit, a source is grounded and a drain is connected to a drain of the second P-type MOS transistor; and a plurality of third N-type MOS transistors in which a gate and a source are grounded and a drain is connected to a drain of the second P-type MOS transistor. The third semiconductor integrated circuit of the present invention also includes an inverter in which an input terminal is connected to the third output node of the second NOR dynamic circuit and the second clock (CLK3) is supplied from an output terminal. In the third semiconductor integrated circuit of the present invention, the plurality of first N-type MOS transistors constituting the first NOR dynamic circuit, and the second N-type MOS transistor and the plurality of third N-type MOS transistors constituting the second NOR dynamic circuit are formed as one circuit block on a semiconductor substrate, and the plurality of first N-type MOS transistors, and the second N-type MOS transistor and the plurality of third N-type MOS transistors are formed in a direction lateral to other adjacent circuit blocks so that diffusion regions constituting sources and drains thereof, and gate electrodes thereof are formed successively, and in the one circuit block, diffusion regions constituting drains of the plurality of first N-type MOS transistors or drains of the second N-type MOS transistor and the plurality of third N-type MOS transistors are formed on an outer side.
In the third semiconductor integrated circuit, it is preferable that in a case where characteristics of diffusion regions are degraded due to a shallow trench insulator (STI) formed between the diffusion regions and the other adjacent circuit blocks, the diffusion regions constituting the drains of the second N-type MOS transistor and the plurality of third N-type MOS transistors are formed on an outer side. Alternatively, it is preferable that in a case where characteristics of diffusion regions are improved due to a shallow trench insulator formed between the diffusion regions and the other adjacent circuit blocks, the diffusion regions constituting the drains of the plurality of first N-type MOS transistors are formed on an outer side.
According to the above-mentioned configuration, in the case where characteristics of the diffusion regions are degraded when the STI is formed, diffusion regions (dummy drain xe2x80x9cdmxe2x80x9d) to be provided as dummies, constituting the drains of the second or third N-type MOS transistors, are formed on an outer side, whereby the degradation of transistor characteristics is compensated. Alternatively, in the case where characteristics of the diffusion regions are improved when the STI is formed, diffusion regions (xe2x80x9cdxe2x80x9d) constituting the drains of a plurality of first N-type MOS transistors are formed on an outer side, whereby transistor characteristics can be enhanced. Because of this, reduction of glitches and lower power consumption can be realized with satisfactory transistor characteristics. Furthermore, the number of inserted dummy gates to be provided as dummies of the second or third N-type MOS transistors can be reduced, and the cell area can be reduced.
In the third semiconductor integrated circuit, it is preferable that diffusion regions constituting sources further are formed on an outer side of the diffusion regions constituting the drains of the plurality of first N-type MOS transistors, or the drains of the second N-type MOS transistor and the plurality of third N-type MOS transistors.
According to the above-mentioned configuration, the number of insertions of dummy gates of the second N-type MOS transistor and the plurality of third N-type MOS transistors becomes equal to the number of gates of the plurality of first N-type MOS transistors that receive a plurality of data A, B, C, and D. This reduces the influence of a miniaturization process (i.e., influence of degeneration of diffusion regions), and lacing due to a signal delay between the drain xe2x80x9cdxe2x80x9d and the dummy drain xe2x80x9cdmxe2x80x9d.
In order to achieve the above-mentioned object, a fourth semiconductor integrated circuit of the present invention includes: a plurality of first NOR dynamic circuits each including: a first P-type MOS transistor in which a gate is supplied with a first clock (CLK1) and a source is connected to a power source; a first switching circuit for receiving a ground potential and a plurality of first data (A1, B1; A2, B2; A3, B3), selectively outputting the ground potential while the first output node is charged, and thereafter, selectively outputting the plurality of data; and a plurality of first N-type MOS transistors in which gates are supplied with an output signal of the first switching circuit, sources are grounded and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed, in order to receive the first clock and the plurality of first data, to hold the charge of the first output node in a case where during one of a period from rising to falling of the first clock and a period from falling to rising of the first clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and to discharge the first output node in a case where at least one of the plurality of first data is not matched. The fourth semiconductor integrated circuit of the present invention also includes a plurality of NAND dynamic circuits for receiving a second dock (CLK2, CLK3) and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second clock and a period from falling to rising of the second clock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held. The fourth semiconductor integrated circuit of the present invention also includes a plurality of second NOR dynamic circuits each including: a second P-type MOS transistor in which a gate is supplied with the first clock and a source is connected to a power source; a second switching circuit for receiving a power source potential and a ground potential, selectively outputting the ground potential while the first output node of the first NOR dynamic circuit is charged, and thereafter, selectively outputting the power source potential; a second N-type MOS transistor in which a gate is supplied with an output signal from the second switching circuit, a source is grounded and a drain is connected to a drain of the second P-type MOS transistor; and a plurality of third N-type MOS transistors in which a gate and a source are grounded and a drain is connected to a drain of the second P-type MOS transistor. The fourth semiconductor integrated circuit of the present invention also includes an inverter in which an input terminal is connected to the third output node of the second NOR dynamic circuit, and the second clock (CLK3) is supplied from an output terminal. In the fourth semiconductor integrated circuit of the present invention, a first circuit block in which the plurality of first N-type MOS transistors constituting the first NOR dynamic circuit are provided, and a second circuit block in which the second N-type MOS transistor and the plurality of third N-type MOS transistors constituting the second NOR dynamic circuit are provided, are formed on a semiconductor substrate so that diffusion regions constituting sources and drains thereof and gate electrodes thereof are formed successively in a direction longitudinal to other adjacent circuit blocks, and the first circuit block and the second circuit block are formed in a lateral direction at an equal interval, and arrangement of the first circuit block and the second circuit block is varied depending upon a distance with respect to the other adjacent circuit blocks.
According to the above-mentioned configuration, degradation and non-uniformity of the diffusion regions are eliminated, and lacing caused by a signal delay between the drains xe2x80x9cdxe2x80x9d of a plurality of first N-type MOS transistors and dummy drains xe2x80x9cdmxe2x80x9d to be provided as dummies of a second N-type MOS transistor and a plurality of third N-type MOS transistors can be reduced.
In the fourth semiconductor integrated circuit, it is preferable that in a case where characteristics of the diffusion regions in the first or second circuit block are degraded due to a shallow trench insulator formed between the diffusion regions and the other adjacent circuit blocks, the second circuit block is disposed on a side at a shorter distance from the other adjacent circuit block.
According to the above-mentioned configuration, in the case where characteristics of the diffusion regions are degraded by the STI formed in a region at a small interval with respect to the other circuit block, a second circuit block to be provided as a dummy is disposed in that region, whereby the characteristics of the diffusion regions in the first circuit block that in receives a plurality of data can be prevented from being degraded.
Alternatively, in the fourth semiconductor integrated circuit, it is preferable that in a case where characteristics of the diffusion regions in the first or second circuit block are improved due to a shallow trench insulator formed between the diffusion regions and the other adjacent circuit blocks, the second circuit block is disposed on a side at a longer distance from the other adjacent circuit block.
According to the above-mentioned configuration, in the case where the characteristics of the diffusion regions are improved by the STI formed in a region having a small interval with respect to the other circuit block, the first circuit block that receives a plurality of data is disposed, and the second circuit block to be provided as a dummy is disposed at a position having a large interval with respect to the other circuit block, whereby the characteristics of the diffusion regions in the first circuit block can be enhanced.
Furthermore, in the fourth semiconductor integrated circuit, it is preferable that diffusion regions constituting sources further are formed on an outer side of the diffusion regions constituting the drains on an outer side in a longitudinal direction of the first and second circuit blocks.
According to the above-mentioned configuration, the influence of a miniaturization process (i.e., influence of degeneration of diffusion regions) can be reduced, and lacing due to a signal delay between the drain xe2x80x9cdxe2x80x9d and the dummy drain xe2x80x9cdmxe2x80x9d can be reduced.
In order to achieve the above-mentioned object, a fifth semiconductor integrated circuit of the present invention includes a plurality of first NOR dynamic circuits each including: a first P-type MOS transistor in which a gate is supplied with a first clock (CLK1) and a source is connected to a power source; a first switching circuit for receiving a ground potential and a plurality of first data (A1, B1; A2, B2), selectively outputting the ground potential while the first output node is charged, and thereafter, selectively outputting the plurality of data; and a plurality of first N-type MOS transistors in which gates are supplied with an output signal of the first switching circuit, sources are grounded and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed, in order to receive the first clock and the plurality of first data, to hold the charge of the first output node in a case where during one of a period from rising to falling of the first clock and a period from falling to rising of the first clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and to discharge the first output node in a case where at least one of the plurality of first data is not matched. The fifth semiconductor integrated circuit of the present invention also includes a plurality of NAND dynamic circuits for receiving a second dock and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second clock and a period from falling to rising of the second clock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held. The fifth semiconductor integrated circuit of the present invention also includes a plurality of second NOR dynamic circuits each including: a second P-type MOS transistor in which a gate is supplied with the first clock and a source is connected to a power source; a second switching circuit for receiving a power source potential and a ground potential, selectively outputting the ground potential while the first output node of the first NOR dynamic circuit is charged, and thereafter, selectively outputting the power source potential; a second N-type MOS transistor in which a gate is supplied with an output signal from the second switching circuit, a source is grounded and a drain is connected to a drain of the second P-type MOS transistor; and a plurality of third N-type MOS transistors in which a gate and a source are grounded and a drain is connected to a drain of the second P-type MOS transistor. The fifth semiconductor integrated circuit of the present invention also includes an inverter in which an input terminal is connected to the third output node of the second NOR dynamic circuit and the second clock is supplied from an output terminal. In the fifth semiconductor integrated circuit of the present invention, among the plurality of first NOR dynamic circuits, the plurality of first N-type MOS transistors constituting each of two first NOR dynamic circuits adjacent in a direction longitudinal to other adjacent circuit blocks are formed on a semiconductor substrate as one circuit block so as to share the second N-type MOS transistor, the plurality of third N-type MOS transistors constituting one of the plurality of second NOR dynamic circuits and the plurality of first N-type MOS transistors, and the second N-type MOS transistor and the plurality of third N-type MOS transistors are formed so that diffusion regions constituting sources and drains thereof and gate electrodes thereof are formed successively in a direction longitudinal to other adjacent circuit blocks.
According to the above-mentioned configuration, two adjacent first NOR dynamic circuits that receive a plurality of data share one second NOR dynamic circuit to be provided as a dummy, whereby a cell area can be reduced and an area of the diffusion regions is increased to prevent degeneration.
In order to achieve the above-mentioned object, a sixth semiconductor integrated circuit of the present invention includes a first NOR dynamic circuit including: a first P-type MOS transistor in which a gate is supplied with a first clock (CLK1) and a source is connected to a power source; a first switching circuit for receiving a ground potential and a plurality of first data (ADR [0-4]), selectively outputting the ground potential while the first output node is charged, and thereafter, selectively outputting the plurality of data; and a plurality of first N-type MOS transistors in which gates are supplied with an output signal of the first switching circuit, sources are grounded, and drains are connected to a drain of the first P-type MOS transistor, whereby the first output node is formed, in order to receive the first clock and the plurality of first data, to hold the charge of the first output node in a case where during one of a period from rising to falling of the first clock and a period from falling to rising of the first dock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and to discharge the first output node in a case where at least one of the plurality of first data is not matched. The sixth semiconductor integrated circuit of the present invention also includes a NAND dynamic circuit for receiving a second clock (CLK2, CLK3) and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the second clock and a period from falling to rising of the second clock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held. The sixth semiconductor integrated circuit of the present invention also includes a second NOR dynamic circuit including: a second P-type MOS transistor in which a gate is supplied with the first clock, and a source is connected to a power source; a second switching circuit for receiving a power source potential and a ground potential, selectively outputting the ground potential while the first output node of the first NOR dynamic circuit is charged, and thereafter, selectively outputting the power source potential; a second N-type MOS transistor in which a gate is supplied with an output signal from the second switching circuit, a source is grounded, a drain is connected to a drain of the second P-type MOS transistor; and a plurality of third N-type MOS transistors in which a gate and a source are grounded and a drain is connected to a drain of the second P-type MOS transistor. The sixth semiconductor integrated circuit of the present invention also includes a first inverter in which an input terminal is connected to the third output node of the second NOR dynamic circuit and the second clock is supplied from an output terminal. The sixth semiconductor integrated circuit of the present invention also includes a compensating circuit for compensating for a voltage drop of the first output node, which is caused by a coupling capacitance formed between the first output node and the second output node, occurring when the second output node is discharged while the charge of the first output node is held. In the sixth semiconductor integrated circuit of the present invention, the compensating circuit includes: a third P-type MOS transistor in which a gate is connected to the second output node and a source is connected to a power source; a fourth P-type MOS transistor in which a source is connected to a drain of the third P-type MOS transistor and a drain is connected to the first output node; and a second inverter in which an input terminal is connected to a drain of the fourth P-type MOS transistor and an output terminal is connected to a gate of the fourth P-type MOS transistor.
According to the above-mentioned configuration, the compensating circuit for compensating for a voltage drop of the output node of the first NOR dynamic circuit due to a coupling capacitance and the first NOR dynamic circuit that functions as a dummy delay circuit are provided. Because of this, an operation speed can be increased and a current path between the power source and the ground of the NAND dynamic circuit is cut off, thereby reducing a leakage current and glitches. Even in the case where the load capacity of the output node of the NOR dynamic circuit is large, a stable operation can be realized at a lower voltage and lower power consumption can be realized.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.